1. Field of the Invention:
This invention generally relates an over-current protection circuit and, more particularly, to an over-current protection circuit especially adapted for protecting a synchronous clock line bus employable in industrial control systems and an industrial system employing same.
2. Description of the related art including information disclosed under 37 C.F.R. 1.97-1.99:
Industrial control systems, such as the parallel bus digital control systems shown in U.S. Pat. No. 4,808,994 issued Feb. 28, 1989, to Riley for "LOGIC INTERCHANGE SYSTEM" and shown in U.S. Pat. No. 5,553,070, issued Sep. 3, 1996, to Riley for "DATA LINK MODULE FOR TIME DIVISION MULTIPLEXING CONTROL SYSTEM", have networks with extensive bus cables. These busses, bus lines, or lines, in an industrial setting, span the factory floor between a host computer or other data termination point and a plurality of data link modules. The data link modules, in turn, are connected with one or more associated controllable devices which are controlled to perform an active function in response to data on the data line or to convey data onto the data line. Because of the factory floor environment, such network bus lines are vulnerable to cuts and resultant short circuits, or shorts.
Accordingly, in such networks it is known to provide over-current protection circuits. These over-current protection circuits detect current in the data bus line circuitry and automatically protectively break the data line circuit in the data bus when the current exceeds a preselected maximum current threshold level to protect the data bus and the associated circuitry.
The data bus, or data line, is an open drain circuit and only conducts current when active. Therefore, excess current in the data line is detected by a current sinking device at an interface circuit, or interface card, only during a clock sync period when all the loads on the data line are inactive, and the total normal load on the data line is known. This enables selection of the correct maximum current threshold level regardless of the number of control modules or the topology in which they are arranged, such as daisy chain, star, loop, loop with branches, trunk, trunk with branches, single branch, etc.
However, the clock line circuit is not open drain but rather has a so-called, totem-pole output that sinks and sources current only at the clock source at the interface card and is free running except during the periodic sync pulse. Consequently, the in-rush current in the charging and discharging of the network clock line varies with the many variations of the wiring topologies and variations in the load. The maximum current threshold level detection method successfully employed with respect to the data line is therefor not well adapted to use with respect to protecting the data line against excessive currents. The level at which the maximum, current threshold level should be set is indeterminate due to the current sinking being performed at the plurality of loads on the line.
Because of this circumstance, the known technique of relying upon absolute current levels to detect a short circuit condition on the clock line results in either false detecting of over-current conditions or in permitting existence of an excess current condition sufficiently long enough to stress the clock driver circuit.
In order to over come this problem, another technique has been known to be employed to prevent over-current conditions in the clock line. In this other technique the clock voltage waveform is monitored to compare the "incoming" clock with the "out-going" clock. The incoming clock is the signal seen on the bus cable at the clock source on the interface card 16. The out-going clock is "expected" clock as generated. Disadvantageously, the implementation of this comparison technique requires complex hardware implementation, exposes the components to destructive excess current, or requires a separate microprocessor to control. This method is also subject to false triggering by electrical noise.